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MO801/MC972 - Topics in Computer Architecture and Hardware: From Logic Gates to AI

In this course, students go through the process of building a computing system from logic gates: designing a processor and a few peripherals, developing the minimal software needed to capture data from those peripherals, running an AI workload on that data, and finally building a hardware accelerator for the resulting algorithm.

Announcements

Date Announcement
03/08 Course starts - see the calendar

Course description

Development of digital circuits with an HDL and their verification; construction of a processor; design of peripherals and their integration with the processor; porting and running a small AI workload on the resulting platform; profiling and hardware acceleration of that workload.

The big picture

The course is organized around a single running example, described in detail in Running Example (TinyML): a small keyword-spotting (KWS) neural network. Every block of the course adds one piece of the system that will eventually run - and then accelerate - this workload:

flowchart LR
    A["Block 1\nSystemVerilog & toolchain"] --> B["Project 1\nYour own RV32I core\non the Tang Nano 9K"]
    B --> C["Project 2\nMemory-mapped peripherals\n+ Zmmul + CMAC + Zicsr"]
    C --> D["TinyML on your CPU\nrun & profile KWS inference"]
    D --> E["Project 3\nHardware accelerator for\nthe profiled bottleneck"]

By the end of the semester, every student will have built - from the gate level up - the processor, the bus, the peripherals, and the accelerator that together run an AI workload on a real FPGA board.

This specific path is one point in a much larger design space - see Design Space & Alternatives for the choices we made (and didn't make) along the way, and how they connect to what real systems do.

Classes

Classes meet twice a week, Monday and Wednesday, at 7PM (19:00). Some sessions are reserved for hands-on lab work on the projects.

Tools and platform

  • Board: Sipeed Tang Nano 9K (Gowin GW1NR-9, ~8.6K LUTs, 64 Mbit on-board PSRAM).
  • Toolchain: OSS CAD Suite - Yosys, nextpnr (himbaechel/Gowin), Verilator, GTKWave, openFPGALoader. Fully open-source, no vendor license required.
  • HDL: SystemVerilog (synthesizable subset for design, full SV for Verilator testbenches).
  • AI framework: TensorFlow Lite Micro for training/exporting the model on a PC; a small hand-written, dependency-free int8 inference kernel for running it on the students' own CPU.

Bibliography

  • Patrick R. Schaumont. A Practical Introduction to Hardware/Software Codesign. 2nd Edition. Springer, 2013. (Main reference for the HW/SW interface block.)
  • Sarah Harris, David Harris. Digital Design and Computer Architecture, RISC-V Edition. Morgan Kaufmann, 2021.
  • David A. Patterson, John L. Hennessy. Computer Organization and Design RISC-V Edition: The Hardware Software Interface. 2nd Edition, 2020.
  • Daniel Situnayake, Jenny Plunkett. AI at the Edge: Solving Real-World Problems with Embedded Machine Learning. O'Reilly, 2023. (TinyML / TFLite Micro reference.)
  • RISC-V Instruction Set Manual (unprivileged ISA).
  • IEEE 1800 - SystemVerilog Language Reference Manual (relevant sections).
  • Conference and journal papers, assigned per seminar topic - see Seminars.

Working in pairs

The three projects are done in pairs: each pair builds one core (Project 1), extends it (Project 2), and accelerates it (Project 3) together, sharing a single Tang Nano 9K board. Pairs are expected to stay the same across all three projects, since the platform carries over from one project to the next. Seminars remain individual - each student in a pair presents on different weeks.

Evaluation

The course grade is composed of:

  • Projects: 80% of the final grade, split across three projects with increasing weight (20% / 30% / 30%) since each project builds on - and is graded together with - the previous one.
  • Seminars: 20% of the final grade. Instead of being concentrated at the end of the semester, one short seminar (~15 min + 5 min Q&A) is presented every week starting in Week 3, on a topic related to that week's block - see Seminars.
  • Exam: there is no written exam.

The exam will be used as a substitute for assessments that took place during excused absences, in accordance with Article 72 of Unicamp's General Undergraduate Regulations.

Grades will be returned in 2 weeks after the oral defense of each project/seminar.

Any form of academic dishonesty during the semester will be punished to the full extent of my authority, including a grade of zero in the course.

Deadlines

  • Project 1: September, 21st
  • Project 2: October, 26th
  • Project 3: November, 30th

Generative AI policy

  • Labs: free use, no declaration required.
  • Projects (1-3) and seminars: use is allowed, but must be declared (one line: used yes/no, where, which tool) in the submitted README/report/slides.
  • Not allowed to be AI-generated, even when declared: the synthesizable SV (datapath, control FSM, accelerator), testbenches, C drivers/glue code, the technical analysis in the Project 3 report, and - for seminars - the paper summary or the "how does this relate to what we are building" connection. AI-assisted debugging, tool-error explanations, and text/language editing are allowed throughout.
  • Verification: every project submission includes a short (~5 min) individual oral defense per pair member on the submitted work; for seminars, the existing Q&A serves this role.
  • Declared use with a solid defense: no penalty. Declared use with a weak defense: graded as such on the relevant rubric criterion. Undeclared use revealed during the defense: handled as academic dishonesty (see above).

Office hours

Office hours: TBD (after class, or by appointment via email).

Calendar

See the calendar for the week-by-week plan.