23 Jul 2020
11:00 Doctoral defense Fully distance
Theme
Improving Hardware / Software Transactional Memory Codesign: A Phased-based and Over-Instrumentation Elimination Approach
Student
João Paulo Labegalini de Carvalho
Advisor / Teacher
Guido Costa Souza de Araujo
Brief summary
The days when computers were considered too luxurious to have at home or when they were just big calculators are over. Currently, computer science and engineering plays a central role in the advances of several research areas. However, meeting the growing demand for performance is still a challenge for computer scientists, as well as for the computer industry. For decades, the microprocessor industry has provided a steady increase in performance with each new generation of processors, following Moore's forecast based on improvements in semiconductor technology. When the limit on power density delivered in semiconductors was close to being reached, the move from mononucleus to multi-core machines proved to be one of the most significant improvements in the performance of modern computers. However, even with greater computational power, parallel machines are still difficult to be adopted due to the challenges of developing parallel programs. Most parallel programming models require programs that explicitly use the available processing cores. However, in order to guarantee correct results, the necessary synchronization in accessing shared resources proved to be a difficult and error-prone task. In this sense, the programming model called Transactional Memory (TM) proposes simplification in writing parallel programs by making synchronization transparent to the programmer. In the TM model the programmer should only be concerned with what should be synchronized and not with the writing of the synchronization code. Even after a large volume of results showing the benefits and performance gains in software, hardware and hybrid systems, the adoption of TM is still restricted to research applications. In fact, recently respected researchers in the field have given up on submitting the revised technical specification to the C ++ language committee to incorporate TM as part of the language. After several unsuccessful attempts, the researchers concluded that there is insufficient data to guide implementation decisions based on experience using the TM model. In addition, conventional hybrid systems (HyTM) have proven to be limited even though they can execute transactions in hardware and software simultaneously. The class of phase-based algorithms (PhasedTM), before the results presented in this manuscript, were considered inferior alternatives to HyTM systems. In this direction, this thesis presents two contributions in the area of TM. First, the thesis builds a solid case in favor of phase-based TM systems. Secondly, the thesis presents an extended support for TM in the Clang compiler that allows the generation of efficient transactional code automatically. More specifically, this thesis presents results that contradict the supposed inferiority of phase-based systems in contrast to conventional hybrid TM systems. The thesis also presents a new annotation mechanism (TMElide) for selective omission of transactional barriers that would normally be inserted unnecessarily by the compiler.
Examination Board
Headlines:
| Márcio Bastos Castro | INE / UFSC |
| Alexandro José Baldassin | DEMAC / UNESP |
| Márcio Machado Pereira | IC / UNICAMP |
| João Pedro Faria Mendonça Barreto | INESC-ID / Portugal |
| Guido Costa Souza de Araújo | IC / UNICAMP |
Substitutes:
| Lucas Francisco Wanner | IC / UNICAMP |
| Sandro Rigo | IC / UNICAMP |
| Hermes Senger | DC / UFSCAR |