03 Apr
14:00 Master's Defense IC3 Auditorium
Integration and performance analysis of parallel RISC-V architectures
Casio Pacheco Krebs
Advisor / Teacher
Supervisor: Lucas Francisco Wanner / Co-supervisor: Guido Costa Souza de Araújo
Brief summary
The use of vector and matrix architectures has the potential for acceleration proportional to the number of primitive processing units and allows reducing the overhead in the instruction cache. In this scenario, accelerating multiplication and accumulation (MAC) routines on regular structures, through parallel processing of data in dedicated hardware structures, has become a desired objective, both by industry and by the academic environment. However, the activation of these structures is not trivial, requiring interventions by the programmer in the base code of the application, otherwise the code will not be reaching the maximum efficiency promoted by the system. In this work, the Hwacha vector coprocessor and the Gemmini matrix accelerator are investigated, concomitantly with the BOOM superscalar RISC-V processor. In order to eliminate the dependency on interventions in the base code and knowledge of activation routines, the SMR automatic code rewriting tool was extended, starting with the development of new libraries, which summarize the preparation and data movement routines, combined with the Hwacha and Gemmini activation instructions in the GEMV and GEMM runtime patterns. With the use of the SMR tool agreed with the Verilator platform, a simulation ecosystem was created, where the separate performance of the Hwacha and the Gemmini were analyzed, and then compared with the RISC-V BOOM processor, from seven applications of the Linear Algebra set of the Polybench benchmark. With this simulation ecosystem, we believe we can provide a tool capable of activating these acceleration structures without the need for interventions in the application's base code.
Examination Board
Lucas Francisco Wanner IC / UNICAMP
Mateus Beck Rutzig DELC/UFSM
Rodolfo Jardim de Azevedo IC / UNICAMP
Ricardo Pannain IC / UNICAMP
Liana Dessandre Duenha FACOM / UFMS