09 out 2023
10:00 Master's Defense IC3 Auditorium
Theme
Exploring Hardware-Software co-design and Dynamic Duty Cycle for energy efficiency in Coherent Transmission ASIC DSP
Student
Lucas de Camargo Barros de Castro
Advisor / Teacher
Rodolfo Jardim de Azevedo - Co-advisor: Lucas Francisco Wanner
Brief summary
In coherent optical transmission systems, the Application-Specific Integrated Circuit \textit{(Application-Specific Integrated Circuit, ASIC)} responsible for doing the Digital Signal Processing (\textit{Digital Signal Processing, DSP}), is the part with the greatest optical transceiver power dissipation. Already at the limit of transistor technologies, in order to reach the limits of energy consumption required by standards and by the market, designers need to look for new opportunities for optimizing designs. This work explores the use of dynamic \textit{Duty Cycle} and Hardware-Software Co-Design techniques seeking to reduce the data processing consumption of such DSP ASICs. The periodic operation characteristic (\textit{duty cycle}) of existing estimation algorithms in these systems is explored to reduce the average consumption of the chip when under favorable conditions, generally improving the consumption of designs originally restricted only to the worst case scenarios. operation. We selected an estimator as a case study, the Carrier Frequency Offset Estimator (\textit{Carrier Frequency Offset Estimator, CFE)}. Using this estimator, a detailed methodology is presented on how to explore energy consumption optimizations for this type of estimation algorithm. The methodology presented includes: the characterization of energy consumption; the creation of a model that describes the effect of Carrier Frequency Offset, the physical impairment that the CFE estimates; the analysis of timing constraints for the period of operation (\textit{duty cycle}); the implementation of three different energy consumption reduction approaches using dynamic duty cycle control and Hardware-Software Co-Design; an analysis of the pros and cons of each approach, focusing on energy consumption reduction, timing and insights on how to apply the methodology to similar algorithms. The best approach for the estimator chosen as a case study, the CFE, obtains, at the post-synthesis simulation level, between 22\% and 74\% reduction in energy consumption, depending on the operating conditions of the system.
Examination Board
Headlines:
| Rodolfo Jardim de Azevedo | IC / UNICAMP |
| Sandro Rigo | IC / UNICAMP |
| Eduardo Rodrigues de Lima | Eldorado |
Substitutes:
| Hervé Cédric Yviquel | IC / UNICAMP |
| Ricardo dos Santos Ferreira | CCE/UFV |