MC542 - Computer Organization: Theory and Practice

Contact Us

Teacher: Rodolfo Jardim de Azevedo (Email)
Monitor: Alexandro Baldassin

Notices

21/11	First Job Notes on the page. Correction results
20/11	Notes from Lab 5 on page. Correction results
19/11	Test scores on the grade board. Labs are still being corrected at the moment. The notes will be released soon.
17/11	Notes delivery forecast: 18/11 on the course page. Reviews: 19/11 at the time of classes in my classroom (Room 10 of the IC)
03/11	Delivery of Lab 5 delayed again. The IC network went down at times during the weekend. New deadline: 04/11 23:59 PM
03/11	Second test scores available on the grade board
30/10	Delivery of Laboratorio 5 postponed until 03/11 until 16:00
17/20	Method to update the Quartus license.
03/10	Classes A and B will not be held on the next Wednesday (08/10). In the class of 03/10 we will decide the new date.
02/10	The classes in room 304 were moved to room 302.
26/09	Lab classes will take place in the CC03 (303) and CC04 (304) rooms as of today.
19/09	The grades of the first test are already in the note board.
12/09	Transparencies on the part of Computer Architecture.
06/09	There will be no class for the afternoon class on Monday (08/09)
12/08	Monitor service hours: Wed: 18h-19h in room 42 of the IC
12/08	Program of the discipline delivered in the first class.
01/08	Copies of transparencies are at Xerox da Mara (Performing Arts)
28/07	Laboratory classes will be held in room 301 during the first weeks of class.
28/07	Important dates: Withdrawal of registration: 04 to 05/09 Course evaluation: 08/10 Last day for registration lock: 13/10 Deadline for the fulfillment of the workload and course programs: 14/11 Study week: 17/11 to 25/11 Final exam period: 26/11 to 01/12

Objectives

Menus

Theory: Basic notions about logic circuits. Memories, central processing units. Addressing, bus, interruption, communications, interfaces and peripherals. Typical computers.
Practice: Digital design methodology. Design techniques using programmable logic. Electrical features of digital circuits. VHDL Language Concepts. Design and implementation of combinational logic (decoders, selectors, etc.). Design and implementation of sequential logic (Flip-flops, Accountants, etc.). Arithmetic circuits. Memories. Design and implementation of a cpu.

Schedules

Classes A and B

Theoretical: Mon: 21h-23h, Wed: 19h-21h (PB03)
Laboratory: Fri: 21 pm-23pm (CC02 and CC03)

Class C

Theoretical: Mon: 16h-18h, Wed: 16h-18h (PB03)
Laboratory: Fri: 16h-18h (CC03)

All classes

Waiters Mon: 18h-19h, Fri: 18h-19h (Room 10 of the IC)
Monitoring: Wed: 18h-19h (Room 42 of the IC)

Evaluation

The evaluation will be given by 3 tests, 1 project and practical work (laboratory).

Exercises

Logical Circuits

Chapter 2: 2.1 to 2.27
Chapter 3: 3.1 to 3.13
Chapter 4: 4.1 to 4.20
Chapter 5: 5.1 to 5.10
Chapter 6: 6.1 to 6.17
Chapter 7: 7.1 to 7.24 (skipping VHDL exercises)
Chapter 8: Skip the VHDL

Computer Architecture

Chapter 2: 2.1 to 2.5; 2.10 to 1.13; 2.15 to 2.22; 2.32; 2.44
Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20; 3.29; 3.30
Chapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
Chapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26

Jobs

REFERENCES

Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill

Chapter 2: 2.1-2.7, 2.9.
Chapter 3: 3.1-3.3, 3.8.8
Chapter 4: 4.1-4.6, 4.12
Chapter 5: 5.1-5.3, 5.5
Chapter 6: 6.1-6.6
Chapter 7: 7.1-7.10
Chapter 8: 8.1-8.5

Peter J. Ashenden. The VHDL Cookbook.
David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface.Morgan Kaufmann

Chapter 1: Read only
Chapter 2: 2.1-2.5
Chapter 3: 3.1-3.8
Chapter 4: 4.1-4.8 (does not include the part already seen in logic circuits)
Chapter 5: 5.15.6

Calendar

30/07	Presentation of the course. Introduction to logic circuits. Logical functions. Boolean algebra [2.1-2.4]
01 / 08S	Equivalence of logical functions. Minterms. Maxterms. Introduction to VHDL [2.5-2.7, 2.9]
04 / 08S	There was no class
06/08	There was no class
08 / 08S	There was no class
11 / 08S	MOSFET transistors: NMOS, PMOS and CMOS. Fan-in and Fan-out [3.1-3.3, 3.8.8]
13/08	Karnaugh Maps: SOP Form [4.1-4.2]
15 / 08S	Karnaugh maps: POS form, don't care on multiple exits [4.3-4.5]
18 / 08S	Transformations for NAND and NOR. Binary, octal, hexadecimal system. Summing circuits. Representation of negative numbers. [4.6, 5.1-5.3]
20/08	Adder / Subtractor, overflow. Multiplexers, implementation of circuits with multiplexers, decoders, demultiplexers. [5.3.2-5.3.5, 6.1-6.2]
22 / 08S	Encoders, code converters, comparators. Basic batch, SR clocked batch, type D batch. [6.3-6.5, 7.1-7.3]
25 / 08S	Latch type D, master-slave flip-flop, D, T and JK flip-flop. Preset and Clear. [7.3-7.7]
27/08	Registers with serial / parallel load and serial / parallel output, counters with enable, clear and parallel load. [7.8-7.10]
29 / 08S	Sequential circuits. Moore machines. [8.1-8.2]
01 / 09S	Mealy machines. [8.3, 8.5]
03/09	Exercises
05 / 09S	Exam 1
08 / 09S	Classes A and B: Introduction to Computer Architecture. Levels of abstraction and technologies [Chapter 1]. Class C: there was no class
10/09	Classes A and B: Performance measures [Chapter 2]. Class C: Introduction to Computer Architecture. Levels of abstraction and technologies.
12 / 09S	Classes A and B: Introduction to VHDL. Class C: Performance measures (Class C)
15 / 09S	Instructions: Machine Language. [Chapter 3]
17/09	Instructions: Machine Language. [Chapter 3]
19 / 09S	VHDL. Delivery of Evidence
22 / 09S	Logical and Arithmetic Unit. [Chapter 4]
24/09	Logical and Arithmetic Unit. [Chapter 4]
26 / 09S	Lab 1: road map
29 / 09S	Processor: Datapath and Control. [Chapter 5]
01/10	Processor: Datapath and Control. [Chapter 5]
03 / 10S	Lab 2: road map
06 / 10S	Processor: Datapath and Control (multicycle implementation). [Chapter 5]
08/10	Classes A and B: There was no class. Class C: Exercises
10 / 10S	Class C: Exam 2. Classes A and B: Lab 3: road map
13 / 10S	Classes A and B: Exercises. Class C: Multicycle Datapath
15/10	Classes A and B: Exam. Class C: Multicycle Datapath Control
17 / 10S	Laboratory 3 e 4.
20 / 10S	Classes A and B: Multicycle datapath. Class C: Pipeline
22/10	Classes A and B: Multicycle datapath. Class C: Pipeline
24 / 10S	Laboratory 5
27 / 10S	Holiday
29/10	Pipeline
31 / 10S	Lab 5 (doubts)
03 / 11S	Classes A and B: Pipeline and Memory Hierarchy. Class C: Memory hierarchy
05/11	Memory hierarchy
07 / 11S	Laboratory 6 e Work 1
10 / 11S	Exercises
12/11	Exam 3
14 / 11S	Laboratory 6 e Work 1
26/11	Examination