30/07 | Presentation of the course. Introduction to logic circuits. Logical functions. Boolean algebra [2.1-2.4] |
01 / 08S | Equivalence of logical functions. Minterms. Maxterms. Introduction to VHDL [2.5-2.7, 2.9] |
04 / 08S | There was no class |
06/08 | There was no class |
08 / 08S | There was no class |
11 / 08S | MOSFET transistors: NMOS, PMOS and CMOS. Fan-in and Fan-out [3.1-3.3, 3.8.8] |
13/08 | Karnaugh Maps: SOP Form [4.1-4.2] |
15 / 08S | Karnaugh maps: POS form, don't care on multiple exits [4.3-4.5] |
18 / 08S | Transformations for NAND and NOR. Binary, octal, hexadecimal system. Summing circuits. Representation of negative numbers. [4.6, 5.1-5.3] |
20/08 | Adder / Subtractor, overflow. Multiplexers, implementation of circuits with multiplexers, decoders, demultiplexers. [5.3.2-5.3.5, 6.1-6.2] |
22 / 08S | Encoders, code converters, comparators. Basic batch, SR clocked batch, type D batch. [6.3-6.5, 7.1-7.3] |
25 / 08S | Latch type D, master-slave flip-flop, D, T and JK flip-flop. Preset and Clear. [7.3-7.7] |
27/08 | Registers with serial / parallel load and serial / parallel output, counters with enable, clear and parallel load. [7.8-7.10] |
29 / 08S | Sequential circuits. Moore machines. [8.1-8.2] |
01 / 09S | Mealy machines. [8.3, 8.5] |
03/09 | Exercises |
05 / 09S | Exam 1 |
08 / 09S | Classes A and B: Introduction to Computer Architecture. Levels of abstraction and technologies [Chapter 1]. Class C: there was no class |
10/09 | Classes A and B: Performance measures [Chapter 2]. Class C: Introduction to Computer Architecture. Levels of abstraction and technologies. |
12 / 09S | Classes A and B: Introduction to VHDL. Class C: Performance measures (Class C) |
15 / 09S | Instructions: Machine Language. [Chapter 3] |
17/09 | Instructions: Machine Language. [Chapter 3] |
19 / 09S | VHDL. Delivery of Evidence |
22 / 09S | Logical and Arithmetic Unit. [Chapter 4] |
24/09 | Logical and Arithmetic Unit. [Chapter 4] |
26 / 09S | Lab 1: Travel Plan |
29 / 09S | Processor: Datapath and Control. [Chapter 5] |
01/10 | Processor: Datapath and Control. [Chapter 5] |
03 / 10S | Lab 2: Travel Plan |
06 / 10S | Processor: Datapath and Control (multicycle implementation). [Chapter 5] |
08/10 | Classes A and B: There was no class. Class C: Exercises |
10 / 10S | Class C: Exam 2. Classes A and B: Lab 3: Travel Plan |
13 / 10S | Classes A and B: Exercises. Class C: Multicycle Datapath |
15/10 | Classes A and B: Exam. Class C: Multicycle Datapath Control |
17 / 10S | Laboratory 3 e 4. |
20 / 10S | Classes A and B: Multicycle datapath. Class C: Pipeline |
22/10 | Classes A and B: Multicycle datapath. Class C: Pipeline |
24 / 10S | Laboratory 5 |
27 / 10S | Holiday |
29/10 | Pipeline |
31 / 10S | Lab 5 (doubts) |
03 / 11S | Classes A and B: Pipeline and Memory Hierarchy. Class C: Memory hierarchy |
05/11 | Memory hierarchy |
07 / 11S | Laboratory 6 e Work 1 |
10 / 11S | Exercises |
12/11 | Exam 3 |
14 / 11S | Laboratory 6 e Work 1 |
26/11 | Examination |