MC542 - Computer Organization: Theory and Practice

Objectives | Schedules | Evaluation | Exercises | Jobs | Bibliography | Calendar | FAQ | Students | Notes

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Teacher: Rodolfo Jardim de Azevedo (Email)
Monitor: Alexandro Baldassin


21/11First Job Notes on the page. Correction results
20/11Notes from Lab 5 on page. Correction results
19/11Test scores on the grade board. Labs are still being corrected at the moment. The notes will be released soon.
17/11Notes delivery forecast: 18/11 on the course page. Reviews: 19/11 at the time of classes in my classroom (Room 10 of the IC)
03/11Delivery of Lab 5 delayed again. The IC network went down at times during the weekend. New deadline: 04/11 23:59 PM
03/11Second test scores available on the grade board
30/10Delivery of Laboratorio 5 postponed until 03/11 until 16:00
17/20Method to update the Quartus license.
03/10Classes A and B will not be held on the next Wednesday (08/10). In the class of 03/10 we will decide the new date.
02/10The classes in room 304 were moved to room 302.
26/09Lab classes will take place in the CC03 (303) and CC04 (304) rooms as of today.
19/09The grades of the first test are already in the note board.
12/09Transparencies on the part of Computer Architecture.
06/09There will be no class for the afternoon class on Monday (08/09)
12/08Monitor service hours: Wed: 18h-19h in room 42 of the IC
12/08Schedule of the discipline delivered in the first class.
01/08Copies of transparencies are at Xerox da Mara (Performing Arts)
28/07 Laboratory classes will be held in room 301 during the first weeks of class.
28/07 Important dates:
  • Withdrawal of registration: 04 to 05/09
  • Course evaluation: 08/10
  • Last day for registration lock: 13/10
  • Deadline for the fulfillment of the workload and course programs: 14/11
  • Study week: 17/11 to 25/11
  • Final exam period: 26/11 to 01/12




Classes A and B

Theoretical: Mon: 21h-23h, Wed: 19h-21h (PB03)
Laboratory: Fri: 21 pm-23pm (CC02 and CC03)

Class C

Theoretical: Mon: 16h-18h, Wed: 16h-18h (PB03)
Laboratory: Fri: 16h-18h (CC03)

All classes

Waiters Mon: 18h-19h, Fri: 18h-19h (Room 10 of the IC)
Monitoring: Wed: 18h-19h (Room 42 of the IC)


The evaluation will be given by 3 tests, 1 project and practical work (laboratory).





30/07Presentation of the course. Introduction to logic circuits. Logical functions. Boolean algebra [2.1-2.4]
01 / 08SEquivalence of logical functions. Minterms. Maxterms. Introduction to VHDL [2.5-2.7, 2.9]
04 / 08SThere was no class
06/08There was no class
08 / 08SThere was no class
11 / 08SMOSFET transistors: NMOS, PMOS and CMOS. Fan-in and Fan-out [3.1-3.3, 3.8.8]
13/08Karnaugh Maps: SOP Form [4.1-4.2]
15 / 08SKarnaugh maps: POS form, don't care on multiple exits [4.3-4.5]
18 / 08STransformations for NAND and NOR. Binary, octal, hexadecimal system. Summing circuits. Representation of negative numbers. [4.6, 5.1-5.3]
20/08Adder / Subtractor, overflow. Multiplexers, implementation of circuits with multiplexers, decoders, demultiplexers. [5.3.2-5.3.5, 6.1-6.2]
22 / 08SEncoders, code converters, comparators. Basic batch, SR clocked batch, type D batch. [6.3-6.5, 7.1-7.3]
25 / 08SLatch type D, master-slave flip-flop, D, T and JK flip-flop. Preset and Clear. [7.3-7.7]
27/08Registers with serial / parallel load and serial / parallel output, counters with enable, clear and parallel load. [7.8-7.10]
29 / 08SSequential circuits. Moore machines. [8.1-8.2]
01 / 09SMealy machines. [8.3, 8.5]
05 / 09SExam 1
08 / 09SClasses A and B: Introduction to Computer Architecture. Levels of abstraction and technologies [Chapter 1]. Class C: there was no class
10/09Classes A and B: Performance measures [Chapter 2]. Class C: Introduction to Computer Architecture. Levels of abstraction and technologies.
12 / 09SClasses A and B: Introduction to VHDL. Class C: Performance measures (Class C)
15 / 09SInstructions: Machine Language. [Chapter 3]
17/09Instructions: Machine Language. [Chapter 3]
19 / 09SVHDL. Delivery of Evidence
22 / 09SLogical and Arithmetic Unit. [Chapter 4]
24/09Logical and Arithmetic Unit. [Chapter 4]
26 / 09SLab 1: Travel Plan
29 / 09SProcessor: Datapath and Control. [Chapter 5]
01/10Processor: Datapath and Control. [Chapter 5]
03 / 10SLab 2: Travel Plan
06 / 10SProcessor: Datapath and Control (multicycle implementation). [Chapter 5]
08/10Classes A and B: There was no class. Class C: Exercises
10 / 10SClass C: Exam 2. Classes A and B: Lab 3: Travel Plan
13 / 10SClasses A and B: Exercises. Class C: Multicycle Datapath
15/10Classes A and B: Exam. Class C: Multicycle Datapath Control
17 / 10SLaboratory 3 e 4.
20 / 10SClasses A and B: Multicycle datapath. Class C: Pipeline
22/10Classes A and B: Multicycle datapath. Class C: Pipeline
24 / 10SLaboratory 5
27 / 10SHoliday
31 / 10SLab 5 (doubts)
03 / 11SClasses A and B: Pipeline and Memory Hierarchy. Class C: Memory hierarchy
05/11Memory hierarchy
07 / 11SLaboratory 6 e Work 1
10 / 11SExercises
12/11Exam 3
14 / 11SLaboratory 6 e Work 1