MC722 - Computer Systems Design

Contact Us

Teacher: Rodolfo Jardim de Azevedo (Email)

Notices

20/12	The notes are on the board. notes. The proofreading review will take place on 21/12 in the classroom at the time of the lesson.
09/12	The work notes are already on the board. notes (the grade of the work is already with the final weight applied, so the maximum value is 1,5).
06/12	The second race will be on PB17.
24/11	All works were delivered correctly and are available for download on the allocation page of groups.
16/11	Notes updated on the page.
14/10	Test 1 will be held in PB17 in the normal schedule. I will not be present on the day, I will send another teacher to apply the test for me.
14/10	There are still students without groups and groups without themes. Please email this information as soon as possible to me. If your RA is not allocated on the groups page or if your group does not have a chosen theme, send a message. The deadline for the work is already defined. There will be no postponement.
30/09	The themes of the works are already available.
28/09	Do not forget to send the composition of the groups by email to me.

Objectives

memory, busbars and input / output systems.
Menu: An introduction to architecture and computer organization. Technologies and historical perspective. Performance measures. Set of instructions. Memory. Arithmetic and logic units. Basic design of a processor. Pipeline. Memory hierarchy: cache and virtual memory. I / O devices.

REFERENCES

• David A. Patterson and John L. Hennessy. Organization and design of computers. The Hardware / Software interface. LTC Publisher
• David A. Patterson and John L. Hennessy. Computer Organization Design, The Hardware / Software Interface. Morgan Kaufmann.

Schedules

Tuesdays and Thursdays: 08: 00-10: 00 (CC01)

Evaluation

The evaluation will consist of 2 tests (P1 and P2) and 1 work (T1).
The semester average (MS) will be calculated using the formula: MS = (4,0 * P1 + 4,5 * P2 + 1,5 * T1) / 10. The student will go for exam (E) if MS <5,0. In this case, the final average (MF) will be calculated as follows: MF = (MS + E) / 2.

Exercises

• Chapter 2: 2.1 to 2.5; 2.10 to 2.13; 2.15 to 2.22; 2.32; 2.44
• Chapter 3: 3.1 to 3.6; 3.9; 3.12; 3.16; 3.20; 3.29; 3.30
• Chapter 4: 4.1 to 4.6; 4.13; 4.17; 4.21; 4.23; 4.25 to 4.28; 4.32; 4.33; 4.40; 4.41; 4.43; 4.44; 4.50; 4.53; 4.57
• Chapter 5: 5.1; 5.4; 5.5 to 5.15; 5.17; 5.18; 5.20; 5.21; 5.22; 5.26
• Chapter 6: 6.1 to 6.4; 6.6; 6.7; 6.9; 6.11 to 6.13; 6.15; 6.21; 6.22; 6.23; 6.26; 6.28; 6.29; 6.30; 6.31
• Chapter 7: 7.1 to 7.9; 7.11; 7.12; 7.20; 7.21; 7.22; 7.22; 7.27; 7.28; 7.31; 7.32; 7.35; 7.38
• Chapter 8: 8.1; 8.2; 8.3; 8.5; 8.7; 8.8; 8.11; 8.12; 8.18; 8.19; 8.22
• Chapter 9: 9.2; 9.5

Jobs

Work should be done by groups maximum of 3 people. Until the end of the semester the work must be presented (the dates will be set later). Each group must choose one of the themes below and send a message by email. The order of registration will be the order of arrival of orders. All papers must have between 10 and 15 pages of text and a presentation of a maximum of 20 minutes (including 5 minutes for questions).
List of works:

• Description of Architectures:
  Follow the same style that the book uses to present the architecture and also indicate the peculiarities of the chosen architecture. Search for the processor ABI, indicate supported operating systems, list the processor family for each architecture.
  • alpha (g10)
  • PA-RISC (g13)
  • ARM (g02)
  • SuperH (g05)
  • M32R
  • AMD 64 (x86 - AMD 64-bit) (g07)
  • Texas TMS320C6x (DSP VLIW) (g12)
  • Intel Itanium (g01)
  • PowerPC (g06)
  • Transmeta Cruso
• General Topics of Computer Architectures:
  If the topic was seen in the classroom, present in more detail, exemplify architectures.
  • Instructional parallelism (superscalar processors, VLIWs, Tomasulo algorithm, etc.) (g14)
  • Thread level parallelism (Hyperthread processors, dual core processors, etc.) (g11)
  • Vector architectures (include use in modern video cards) (g04)
  • Multimedia extensions to processor instruction sets (MMX, SSE, SSE2, 3DNow, etc.) (g09)
  • 16-bit instruction sets for 32-bit processors (ARM Thumb, MIPS 16, etc.) (g15)
  • Languages ​​for describing architectures (LISA, nML, EXPRESSION, ArchC, ISDL, etc.) (g08)
  • Virtual machine architectures (Java, .NET, JIT techniques, etc. Focus on architectures over APIs) (g03)

Evaluation criteria:

• Redaction: Weight 20%. Possible grades: Bad (0,0), Satisfactory (5,0) and Good (10,0)
• Content: Weight 40% (scope of text, level of detail, correctness, etc.)
• Presentation: Weight 40%. (scope of the presentation, level of detail, correctness, etc.) Only one student in the group should make the presentation on behalf of the group and he will be drawn at the time

Calendar

August
19/08 Q	Presentation of the Course. Introduction (Chap. 1). Sample files: program1.c e program2.c
24 / 08 T	Performance measures (2.1, 2.2 and 2.3)
26/08 Q	Performance measures
31 / 08 T	Set of Instructions
September
02/09 Q	Set of Instructions
07 / 09 T	Holiday
09/09 Q	There was no class
14 / 09 T	Computational Arithmetic (integers)
16/09 Q	Computational Arithmetic (integers)
21 / 09 T	Computational Arithmetic (integers and floating point)
23/09 Q	Exercises
28 / 09 T	Chapter 5: Datapath
30/09 Q	Datapath unicycle
October
05 / 10 T	Datapath unicycle / multicycle
07/10 Q	Multicyclepath datapath
12 / 10 T	Holiday
14/10 Q	Chapter 6: Pipeline
19 / 10 T	Pipeline
21/10 Q	Pipeline
26 / 10 T	Exercises
28/10 Q	Test 1 (PLEASE NOTE: The test will be in room PB17)
November
02 / 11 T	Holiday
04/11 Q	Memory Hierarchy
09 / 11 T	Caches
11/11 Q	Virtual Memory
16 / 11 T	Input and Output
18/11 Q	Input and Output
23 / 11 T	Chapter 9
25/11 Q	Chapter 9
30 / 11 T	Presentations: g01, g02, g05, g06
December
02/12 Q	Presentations: g07, g10, g12, g13
07 / 12 T	Presentations: g04, g09, g11, g14
09/12 Q	Presentations: g03, g08, g15. Exercises
14 / 12 T	Exercises
16/12 Q	Test 2 (PLEASE NOTE: The test will be in room PB17)
21 / 12 T	Delivery of notes and review
January
06/01 Q	Examination