MO801/MC912

Topics in Architecture and Hardware

Objectives
 classrooms Project Manager Assessment Jobs REFERENCES Calendar FAQ Students Notes

Faculty

Notices

Data
 Notice
06/06/03
 The testbench for Job 2 has been updated to suppress dependency when inserting coins in sequence. Attention to the fact that the command c 3 5 followed by the s 8 00000 in testbench means passing a BRL 0,01 coin with a glitch in the sensor of R$0,05.
05/06/03
 An implementation of the first job.
04/06/03
 the compiler ghdl is installed in the area of gpsl in the IC. It is a VHDL compiler based on gcc. As a result of the compilation it generates an executable file. Example of usage for the first job:
USE_GCC=1 . ~gpsl/configure_area.sh
ghdl -a --ieee=synopsys arbiter.vhd
ghdl -a --ieee=synopsys tb_arbiter.vhd
ghdl -e --ieee=synopsys tb_arbiter
tb_arbiter
The first two lines compile the code, the third generates the executable (tb_arbiter is the name of the highest level entity) and the fourth line executes the generated program, which is the testbench.
04/06/03
 Result 2. Look in detail at the comments provided. Please send updated versions as soon as possible.
20/05/03
 Included frequently asked questions in the FAQ
20/05/03
 Two interesting texts about projects: 1 e 2.
20/05/03
 Added one more clock signal in job 3
20/05/03
 Result from work 1
08/04/03
 New Testbench for the first available job. Work delivery date: 25/04/03.
01/04/03
 A preliminary Testbench for the first job is now available.
26/03/03
 If you do not have an Ocelot account or a password to access one of the course accounts, contact one of the professors.
21/02/03
 Confirmed classroom: CC05.
19/12/02
 Home page version available.

Objectives

In this discipline will be studied:
  • Hardware Description Language (VHDL)
  • Leon processor architecture (compatible with SPARC V8 model)
  • AMBA Peripheral Interconnect Bus (used by Leon)
  • Circuit synthesis and simulation tools from Mentor, Xilinx and Altera
  • Methodology for development and reuse of hardware components (IP colors)

classrooms

Tuesdays and Fridays 10:00 - 12:00
Room: CC05
Project Manager

Get in touch whenever necessary. If you prefer to make an appointment, make arrangements via email.



Assessment

The evaluation will be based on the 4 works.
Jobs

Students will form groups and each group will have the final work to implement one or more peripherals for the Leon and the XESS XSV800 board.
Work 1: bus arbiter (delivery 25/04)
Work 2: coin counter (06/05 delivery)
Work 3: UART (delivery 26/05)
Work 4: Hardware module for the Leon (delivery 07/07)

REFERENCES

Material used in the course (also available on the IC network at ~rodolfo/pub):

Calendar

February
Day Matter
18T
 Course Presentation. Introduction to Hardware Design.
21S
 VHDL: Basic Topics.
25T
 VHDL: Basic Topics (archive).
28S
 VHDL: Basic topics and lab practice.
March
Day Matter
07S
 VHDL: Basic Topics and Laboratory Practice (archive).
11T
 VHDL: Basic Topics (archive).
14S
 VHDL: Component instantiation.
18T
 Introduction to Leon (archive).
21S
 Lion.
25T
 Mentor simulation and synthesis tools.
28S
 VHDL: Components and Settings.
April
Day Matter
01T
 OCP: Overview (archive).
04S
 Introduction to testbenches (example: testbench of work 1).
08T
 VHDL: Functions, Procedures (archive).
11S
 VHDL: bit_vector, guard, buffer (archive) (examples).
15T
 Service/Work
18S
 Holiday
22T
 Service/Work
25S
 Service/Work
29T
 Service/Work
May
Day Matter
02S
 Holiday
06T
 Service/Work
09S
 Service/Work
13T
16S
20T
23S
27T
30S
June
Day Matter
03T
06S
10T
13S