MO801/MC912

Topics in Architecture and Hardware

First job

The first job is to implement an arbitrator with 4 Appetizer. The referee must use round-robin discipline to manage priorities. Use the entity below:

entity arbitrator is
    port (clk : in bit;
	     resetn : in bit;
	     request : in bit_vector (0 to 3);
             acknowledge : out bit_vector (0 to 3)
	    );
end entity arbitrator;

All names must be identical to those described above. Use the following convention for signals:

clk	Active clock on rising edge
reset	Circuit reset, active at zero. When it occurs, the request(0) receives priority
request	Bus request vector
acknowledge	Response vector to bus requests

Your code must be compiled and simulated using Mentor's tools (qvhcom and qhsim). In your circuit there must always be a bus line with maximum priority and the priority will decay sequentially from it for all other signals. every time a acknowledge is provided, the highest priority line will change. See some examples:

Line of highest priority	Request (0, 1, 2, 3)	acknowledge (0, 1, 2, 3)	new line of highest priority
0	1000	1000	1
1	1100	0100	2
2	1100	1000	1
1	1100	0100	2
2	1111	0010	3
3	1111	0001	0

Note that there is only a maximum of one signal on the bus. acknowledge active at every moment.

testbench

Testbench is composed of the following files:

tb_arbiter.vhd: VHDL module that implements Testbench.
arbiter.input: Input file for Testbench. Each line of this file contains a value for the input signals (clk, resetn and request)
referee.expected: Expected output file.
Each line of this file contains an expected Acknowledge value (4 bits) for that request.
test.do: Command file for qhsim.
gen_tb.c: File that generates an arbiter.input. ATTENTION: part of the generated file is formed by a sequence of random tests.
makefile: File to simplify Testbench compilation. To run Testbench, type make testbench

To run Testbench, put all the above files in a directory along with your vhdl module, which should be called arbiter.vhd, and run make testbench. Various compilation and simulation messages will appear on your screen.
At the end of the process, the message should appear: "0 error(s) in simulation". If an error appears, look at the file arbiter.output that was generated by Testbench and see the difference between it and the referee.expected. Run the simulator (qhsim) manually and view the waveforms to debug your module.