MO801/MC912

Topics in Architecture and Hardware

Third Job

This work can be done in pairs.
Implement a 8250 UART.

Interface

The Circuit Interface must be compatible with the OCP 1.0 model

entity Uart is
  port (Clk : in std_logic; -- Clock OCP
        Reset_n : in std_logic; -- OCP sideband
        MAddr : in std_logic_vector(2 downto 0);
        MCmd : in std_logic_vector(2 downto 0);
        MData : in std_logic_vector(7 downto 0);
        SCmdAccept : out std_logic;
        SData : out std_logic_vector(7 downto 0);
        SResp : out std_logic_vector(1 downto 0);
        SInterrupt : out std_logic; -- OCP sideband;
	  -- External UART signals
        ClkBase : in std_logic; -- Clock for UART
        RxD : in std_logic; 
        TxD : out std_logic;
        RTS :out std_logic;
        CTS : in std_logic;)
       );
end entityUart;

Consider the ClkBase signal to be 1.843.200Hz (=16×115.200Hz)

Internal Recorders

Registrar	Function	Address	Access	Default
TxD	Transmission buffer; access if DLAB=0	0	writing	-
RxD	Receive buffer; access if DLAB=0	0	reading	-
BAL	Lesser significant divider; access if DLAB=1	0	bidirectional	02 h
BAH	Most significant divider; access if DLAB=1	1	bidirectional	00 h
IIR	Enable interrupts; access if DLAB=0	1	bidirectional	00 h
IIR	Interrupt Identifier	2	reading	01 h
LCR	Initializes UART operation; contains the DLAB bit	3	bidirectional	00 h
MCR	Modem controller; commands OUT2	4	bidirectional	00 h
LSR	Operation status	5	reading	60 h
MSR	Modem Status	6	reading	00 h
SCR	Port detection recorder	7	bidirectional	00 h

It is not necessary to implement modem functionality, but registers must be implemented and unused bits must be kept at default values.
A simplified description of 5 sheets in Portuguese was placed in the xerox on each of these registers.

testbench

Implement a Testbench for your circuit. Test as many cases as you deem necessary to prove the specified functionality.

Synthesis

Your circuit must be synthesizable with Leonardo. Test it out before handing in the work. For synthesis, use the FPGA Xilinx Virtex v800hq240-4.

Report

Submit a short report about the work.