MO801 / MC912 - Job 1: Coin Counter

Objective

The first job is to implement a currency counter circuit restricted to the old currencies of R $ 0,01, R $ 0,05, R $ 0,10, R $ 0,50 and R $ 1,00.

Coin Counter Sensor Scheme

Use the entity below:

entity counter is generic (niclos: positive: = 7); port (clk: in std_logic; resetn: in std_logic; sensor: in std_logic_vector (0 to 4); total: out natural); end entity counter;

All names must be identical to those described above. Use the following convention for signs:

niches	Number of cycles to consider the input signal stable (see details on the debounce below)
clk	Active clock on rising edge
reset	Circuit reset, active at zero. When a reset occurs, the total value must be changed to zero
sensor	Sensor signals vector. sensor (i) = '1' means that there is an object blocking the i-th sensor.
total	Total amount so far. The total amount must be updated whenever, and only when, the currency finishes passing through the sensors.

Your circuit must be synchronous and make changes to the output on the clk upward pulses.

debounce

All signals from sensors can undergo unwanted oscillations during transitions. These oscillations must be removed through a special circuit to debounce the signal. To eliminate them, the debounce circuit should only consider a signal that has the same value stable for n successive cycles. Make your circuit configurable (use generic).

Example

The figure below shows an example of entries for the coin counter: Coin Counter Example

Please note the following details:

Sensor 4 cannot be considered if we work with more than 3 debounce cycles (in blue);
Sensor 0 will not be considered for the second time if we work with more than 2 debounce cycles (in yellow);
Counting the coin should only be done at the time indicated in green (assume in this case that the debounce is done with niclos = 3).

In this example, given that sensor 3 has been stable for more than 7 cycles = 0,50 cycles, the currency counted is R $ XNUMX (the green case is just an example and the actual count should happen later).

testbench

Here are two Testbenches for this job. Here is a brief description of each along with the necessary files:

Simple Testbench

This Testbench is a simplified version, but sufficient for many simple hardware modules like this. It only reads from the input file the signal values in each time unit and provides these inputs for the module to be tested at the same time that it collects the outputs and writes to two other files: one only with the time and the exit and the other also with the entrance.
Files: tb_contador_base.vhd, counter.base.input, counter.base.expected.
The file tb_contador_base.vhd should be used as the highest level entity in your project.

Detailed Testbench

This Testbench is capable of receiving commands from the configuration file. Note that, from the previous Testbench, the entry would be extremely repetitive, so this version allows commands to be specified such as:

Command	Description
r	Activates the reset signal for 8 clock cycles
s sensor_value cycles	During clock cycles they keep the sensors with the specified value (sensor_value)
c coin cycles	Simulates the insertion of a coin of coin value, making all necessary transitions and spending niches between each new value

Although this summer it is simpler to implement a large number of tests, more programming time is needed to develop the Testbench module.
Files: tb_counter.vhd, counter.input, accountant.expected.
The file tb_contador.vhd should be used as the highest level entity in your project.