MO801 / MC912 - Topics in Architecture and Hardware (Design of Advanced Digital Circuits)

Notices

11/07	Final notes on the grade board.
04/07	The notes should be released by the end of this week.
09/06	12/06 class in room 96. 14/06 class in room 303 of IC-3.
06/06	Class in room 303 of IC-3. Get the implementations in the ~ rodolfo / mo801 / implementacao_t2 directory. Attention: try not to look at the source code.
29/05	Debt class at Work 2 in room 303 of IC-3.
24/05	Define the themes of Work 3 in the wiki:
17/05	There will be no summary to be delivered on 24/05.
17/05	Job Feedback 1.
04/05	Preliminary result of work 1. Attention: As stated, the results are preliminary.
20/04	The IC3 entry permit for special students is already in the IC3 ordinance. The accounts are already open and you need to sign a term of commitment and withdraw them in the IC3 administration.
17/03	Whenever you send files to me, put only the 6 digits of the RA as a name, followed by the type of the file (.pdf, .tgz, ...) in lower case. This makes my job much easier.
13/03	Only for the first and second deliveries, I will confirm receipt of all emails received.
08/03	The book "The Designer's Guide to VHDL" must be available at Livraria da Qu mica with an estimated value of R $ 90,00. The book "Comprehensive Functional Verification - The Complete Industry Cycle" has an estimated value of R $ 75,00 (10 orders are required to confirm the price and order). Phones: 3288-0048 / 3788-3403.
30/07	Check the important dates on Postgraduate calendar and graduation calendar.

Objectives

Develop skills related to the design of integrated digital circuits that include: description of the circuit in VHDL, circuit test, flows and simulation tools, synthesis and analysis of energy consumption.

REFERENCES

Books:

• Peter J. Ashenden. The Designer's Guide to VHDL. 2nd Edition. Morgan Kaufmann Publishers. 2002. Main Bibliography.
  
• Bruce Wile, John C. Goss, Wolfgang Roesner.  Comprehensive Functional Verification - The Complete Industry Cycle. Morgan Kaufmann Publishers. 2005. Recommended reading.
• Douglas J. Smith. HDL Chip Design. Doone Publications. 2001.
• Stephen Brown and Zvonko Vranesic. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill
• John P. Uymura. Digital Systems - An Integrated Approach. Thomson Pioneer. 2002.

Articles, manuals and specifications of standards for reading during the semester will also be recommended.

Recommended development tools for the first phase of the course: GHDL e Quartus II web.

Activities

All activities are mandatory delivery. The final average of the discipline will be proportional to the number of activities delivered. An activity with a score greater than or equal to 5 will be considered delivered.

Listing with files of submissions that I have already recorded on my computer.

Abstracts

• Activity 1: Summary of a page about FPGA. What is it? Features? How it works? etc ... Delivery until 8:00 de 15/03/06. Email Subject: MO801: Delivery R1 - RA_number
• Activity 2: Summary of a page about the FPGA Altera Stratix II: Features, functionality, organization, capacity, etc ... Delivery by 8:00 de 22/03/06. Email Subject: MO801: R2 Delivery - RA_Number
• Activity 3: Summary of a page about the FPGA Altera Cyclone II: Features, functionality, organization, capacity, etc ... Delivery by 8:00 de 29/03/06. Email Subject: MO801: R3 Delivery - RA_Number
• Activity 4: Summary of a page about the FPGA Xilinx Virtex 4: Features, functionalities, organization, capacity, etc ... Delivery by 8:00 de 05/04/06. Email Subject: MO801: R4 Delivery - RA_Number
• Activity 5: Summary of a page about the FPGA Xilinx Spartan III: Features, functionality, organization, capacity, etc ... Delivery by 8:00 de 12/04/06. Email Subject: MO801: R5 Delivery - RA_Number
• Activity 6: Summary of a page about the article: "Hardware Speech Recognition for User Interfaces in Low Cost, Low Power Devices ", Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer, DAC 2005. Delivery until 8:00 de 19/04/06. Email Subject: MO801: R6 Delivery - RA_Number
• Activity 7: Summary of a page about an article from DAC 2005. Make your reservation here. Delivery until 8:00 de 26/04/06. Email Subject: MO801: R7 Delivery - RA_Number
• Activity 8: Summary of a page about the article: "Automatic insertion of gated clocks at register transfer level", N. Raghhavan, V. Akella, and S. Bakshi. Proceedings of 12th Int.l Conf. on VLSI Design, January, 1999. Delivery until 8:00 de 03/05/06. Email Subject: MO801: R8 Delivery - RA_Number.
• Activity 9: Summary of a page about the article: "Reducing switching activity on datapath buses with control-signal gating", H. Kapadia, L. Benini, and G. De Micheli, IEEE J. Solid-State Circuits, vol. 34, pp. 405-414, Mar. 1999. Delivery until 8:00 de 10/05/06. Email Subject: MO801: R9 Delivery - RA_Number.
• Activity 10: Summary of a page about the article: "Orthogonal partitioning and gated-clock architecture for low-power realization of FSMs", R. Shelar and MP Desai, IEEE ASIC / SOC'2000, pp. 266-270, Sept, 2000. Delivery until 8:00 de 17/05/06. Email Subject: MO801: R10 delivery - RA_number.

Presentations

Each student must make a presentation during the semester. The themes of the presentations will be listed in due course. Students can volunteer for the topics. The presentations will last for 30 minutes and will be made at the end of the classes indicated in the calendar.

List of themes:

• FPGA Altera Stratix II - Jo o Paulo Porto
  
• FPGA Altera Cyclone II - Juliano Coimbra
• FPGA Xilinx Virtex 4 - Vinicius Jos Latorre
• FPGA Xilinx Spartan III - Jo o Fabio Pegorin Di Lello
• AMBA Bus (2.0 and 3.0) - Denis Santos
• CoreConnect Bus - Fabiana Bellette Gil
• Avalon Bus - Felipe Portavales Goldstein
• OCP / IP - Sergio Ordine
• Nios - P ricles Lima
  
• Microblaze - Josu Tzan Hsin Ma
• Altera DSP Builder (focus: tutorial on functionality and use) - Michele Tamberlini
• Altera SignalTap (focus: tutorial on functionality and use) - Henrique Dante
• SystemC class library - Roberto Gallo
  
• SystemVerilog Language - Bruna Chesye Dias
• Verilog Language - Wendel Assis
  
• Vera Language

Jobs

Each student must do the following tasks individually:

• Work 1: Quadrature Counter. Delivery until 8:00 de 28/04/06. Email Subject: MO801: Delivery T1 - RA_Number.
• Work 2: Small Processor. Delivery until 8:00 de 02/06/06. Email Subject: MO801: Delivery T2 - RA_Number.
• Work 3: Define the theme in wiki. Delivery until 8:00 de 28/06/06. Email Subject: MO801: Delivery T3 - RA_Number.

Calendar

06 / 03S	Course Presentation, Introduction and Review of Logical Circuits	Presentation.ppt (pdf)
08/03	Review of Logical Circuits	CircuitoLogicos.ppt (pdf)
13 / 03S	Introduction to VHDL	VHDL.ppt (pdf)
15/03	Introduction to VHDL
20 / 03S	VHDL Coding Style	CodingStyle.ppt (pdf)
22/03	Coding for Performance	Performance.ppt (pdf)
27 / 03S	Tests	Tests.ppt (pdf)
29/03	There will be no class
03 / 04S	Circuit modeling tips. Presentation: Stratix II	TipsCircuits.ppt (pdf)
05/04	Complete Example: MAC. Presentation: Avalon Bus	MAC.ppt (pdf)
10 / 04S	Continuation of MAC. Presentation: Cyclone II
12/04	Subprograms. Presentation: AMBA Bus	Subprograms.ppt (pdf)
17 / 04S	Components, configurations and generate. Presentation: Virtex 4	Big Projects.ppt (pdf)
19/04	Leon2 processor. Presentation: CoreConnect bus	Leon2.ppt (pdf)
24 / 04S	Energy consumption. Presentation: Spartan 3	LowPower.ppt (pdf)
26/04	Energy Consumption, Debts, Quartus II. Presentation: OCP / IP
01 / 05S	There will be no class
03/05	Check. Presentation: Microblaze	Verification.ppt (pdf)
08 / 05S	Comments on work 1, work 2, Check.
10/05	OCP / IP review. Changes DSP Builder	OCP.ppt (pdf)
15 / 05S	Check. Alter SignalTap
17/05	Class in room 303 of IC-3 - Questions about Work 2
22 / 05S	Verification by Simulation (testbenches). Nios II	VerificationSimulacao.ppt (pdf)
24/05	Coding Style Review
29 / 05S	VHDL (other topics)	VHDL2.ppt (pdf)
31/05	Class in room 303
05 / 06S
07/06
12 / 06S
14/06
19 / 06S
21/06
26 / 06S
28/06
03 / 07S
12/07	MC912 exam