ac_regbank.H

/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- */

/*  ArchC Storage Library for the ArchC architecture simulators
    Copyright (C) 2002-2004  The ArchC Team

    This library is free software; you can redistribute it and/or
    modify it under the terms of the GNU Lesser General Public
    License as published by the Free Software Foundation; either
    version 2.1 of the License, or (at your option) any later version.

    This library is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    Lesser General Public License for more details.
*/

/********************************************************/
/* The ArchC storage device base class.                 */
/* Author:  Sandro Rigo                                 */
/*                                                      */
/*                                                      */
/* The ArchC Team                                       */
/* Computer Systems Laboratory (LSC)                    */
/* IC-UNICAMP                                           */
/* http://www.lsc.ic.unicamp.br                         */
/********************************************************/



#ifndef _AC_REGBANK_H
#define _AC_REGBANK_H

#include "ac_storage.H"

class ac_resources;
  
template<class T>class ac_regbank: public ac_storage {
public:
  
  T read( unsigned address ){

#ifdef AC_STATS  
    ac_resources::ac_sim_stats.add_access(name);
#endif

    return *((T *)(Data+((address)*sizeof(T)))); 
  }

  ac_Dword read_double( unsigned address ){

#ifdef AC_STATS  
    ac_resources::ac_sim_stats.add_access(name);
#endif

    return *((ac_Dword *)(Data+((address)*sizeof(ac_word)*2))); 
  }


  void write( unsigned address , T datum  ){
#ifdef AC_MEM_HIERARCHY
    if(ac_resources::ac_wait_sig)
      return;
#endif
  
#ifdef AC_UPDATE_LOG
    changes.push_back( change_log(address, datum , sc_simulation_time()));
#endif
  
    *((T *)(Data+((address)*sizeof(T)))) = datum;
  
#ifdef AC_STATS
    ac_resources::ac_sim_stats.add_access(name);
#endif
  }


#ifdef AC_DELAY

  void write( unsigned address , T datum, unsigned time ){
    delays.push_back( change_log( address, datum, (time * ac_resources::time_step) + ac_resources::time_step + sc_simulation_time()));
  }
#endif

  ac_regbank( char* name, unsigned size=sizeof(T) ):ac_storage(name,size*sizeof(T)){}

  void load( char* file ){

    ifstream input;
    string read;
    string word;
    T data;
    istringstream line;

    bool is_addr;

    int  addr=0;

    // Looking for initialization file.
    input.open(file);
    if(!input){
      AC_ERROR("Could not open input file:" << file);
    }
    else{
      
      while( !input.eof() ){

        line.clear();
        getline(input, read);
        line.str(read);
                        
        is_addr = 1;

        //Processing line
        while(line >> word){

          if( word == ".text" ){
            AC_ERROR("Should not load code into the register bank: " << name);
            return;
          }
                                                
          if( word == ".data" ){
            continue;
          }

          //Processing word
          if( is_addr ){
            addr = strtol(word.c_str(), NULL, 16);
            is_addr = 0;
          }
          else{
            data = (T)strtol( word.c_str(), NULL, 16);
            write(addr,data);
            addr+= sizeof(T);
          }
        }
      }
    }
  }
};

#endif //_AC_REGBANK_H

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