entity Uart is
  port (Clk        : in  std_logic; -- Clock OCP
        Reset_n    : in  std_logic; -- OCP sideband
        MAddr      : in  std_logic_vector(2 downto 0);
        MCmd       : in  std_logic_vector(2 downto 0);
        MData      : in  std_logic_vector(7 downto 0);
        SCmdAccept : out std_logic;
        SData      : out std_logic_vector(7 downto 0);
        SResp      : out std_logic_vector(1 downto 0);
        SInterrupt : out std_logic; -- OCP sideband;
	  -- Sinais externos da UART
        ClkBase    : in  std_logic; -- Clock para a UART
        RxD        : in  std_logic; 
        TxD	   : out std_logic;
        RTS        : out std_logic;
        CTS        : in  std_logic;)
       );
end entity Uart;