01/03: Artigos selecionados para apresentação neste semestre.
01/03: Não perca das datas importantes do Calendário de graduação e Calendário de pós-graduação.
Revisar a literatura das áreas de Arquitetura de Computadores e Compiladores através de artigos recentes.
Artigos selecionados para apresentação neste semestre.
Artigos recentes das áreas de Arquitetura de Computadores e Compiladores.
A avaliação é baseada nas apresentações, presença e participação em sala.
Para graduação: NotaFinal = 0,5 * NotaApresentação + 0,5 * NotaParticipação.
Para pós-graduação: Conceitos: S: presença >= 75%, I: presença < 75%.
Qualquer tentativa de fraude durante o semestre será punida até o limite da minha autoridade, incluindo nota zero na disciplina para todos os envolvidos.
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| Data | Aula | Artigo | Apresentador |
|---|---|---|---|
| 02/03 | 1 | Apresentação | |
| 09/03 | 2 | Locality-Oblivious Cache Organization leveraging Single-Cycle Multi-Hop NoCs. Woo Cheol Kwon (MIT); Tushar Krishna (MIT); Li-Shiuan Peh (MIT). ASPLOS 2014. | Jorge Gonzales |
| 16/03 | 3 | Improving the Energy Efficiency of Big Cores. Kenneth Czechowski (Georgia Institute of Technology), Victor W. Lee (Intel), Ed Grochowski (Intel), Ronny Ronen (Intel), Ronak Singhal (Intel), Richard Vuduc (Georgia Institute of Technology), Pradeep Dubey (Intel). ISCA 2014. | Thiago Rocha |
| 23/03 | 4 | The Benefit of SMT in the Multi-Core Era: Flexibility towards Degrees of Thread-Level Parallelism. Stijn Eyerman (Ghent University); Lieven Eeckhout (Ghent University). ASPLOS 2014. | Marcos Barros |
| 30/03 | 5 | Exploiting Thermal Energy Storage to Reduce Data Center Capital and Operating Expenses. Wenli Zheng (The Ohio State University), Kai Ma (The Ohio State University), Xiaorui Wang (The Ohio State University) . HPCA 2014. | Cláudio Silva |
| 06/04 | 5 | Skewed Compressed Cache. Somayeh Sardashti (University of Wisconsin - Madison), Andre Seznec (INRIA), David Wood (University of Wisconsin - Madison). MICRO 2014. | Rafael Sousa |
| 13/04 | 6 | Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures. Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David Brooks (Harvard University). ISCA 2014. | Priscila |
| 20/04 | - | Não haverá aula | |
| 27/04 | 7 | Improving Cache Performance by Exploiting Read-Write Disparity. Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jimeenez. HPCA 2014. | Mirela |
| 04/05 | 8 | PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. Lockhart, D.; Zibrat, G.; Batten, C.. MICRO 2014. | Carlos Petry |
| 11/05 | 9 | Load Value Approximation. Joshua San Miguel, Mario Badr, and Natalie Enright Jerger. MICRO 2014. | Gustavo Henrique Czaikoski |
| 18/05 | 10 | Efficient Memory Virtualization. Jayneel Gandhi (University of Wisconsin - Madison), Arkaprava Basu (AMD), Michael M. Swift (University of Wisconsin - Madison), Mark D. Hill (University of Wisconsin - Madison) | Daniel Góes |
| 25/05 | 11 | The Dirty-Block Index. Vivek Seshadri (Carnegie Mellon University), Abhishek Bhowmick (Carnegie Mellon University), Onur Mutlu (Carnegie Mellon University), Phillip B. Gibbons (Intel Pittsburgh), Michael A. Kozuch (Intel Pittsburgh), Todd C. Mowry (Carnegie Mellon University). ISCA 2014. | Raoni |
| 01/06 | 12 | Micro-Policies: Formally Verified, Tag-Based Security Monitors | Arthur Azevedo de Amorim |
| 08/06 | 13 | Shrink: Reducing the ISA Complexity Via Instruction Recycling. Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, Rodolfo Azevedo. ISCA-2015 | Rafael Auler |
| 15/06 | 14 | Seismic Wave Propagation Simulations on Low-power and Performance-centric Manycores The vast data processing capabilities needed by seismic wave propagation simulations make HPC architectures a natural choice for their execution. However, the evolution of their power efficiency did not follow the pace of their evolution in performance. As a response to this divergence, energy-efficient and low-power processors began to make their way into the market. In this paper we employ a novel low-power processor, the MPPA-256 manycore, to perform seismic wave propagation simulations. It has 256 cores connected by a NoC, no cache-coherence and only a limited amount of on-chip memory. We describe how its architectural idiosyncrasies influenced our solution for an energy-efficient implementation. As a counterpoint to the low-power MPPA-256 architecture, we employ Xeon Phi, a performance-centric manycore. Although both processors share some architectural similarities, the challenges to implement an efficient seismic wave propagation kernel on these platforms are very di↵erent. In this work we compare the performance and energy efficiency of our implementations for these processors to proven and optimized solutions for other hardware platforms such as general-purpose processors and a GPU. Our experimental results show that MPPA-256 has the best energy efficiency, consuming at least 77 % less energy than the other evaluated platforms, whereas the performance of our solution for the Xeon Phi is on par with a state-of-the-art solution for GPUs. | Emílio |
| 22/06 | |||
| 29/06 |