Retrospective: From Gates to AI

Rodolfo Azevedo

Institute of Computing, University of Campinas (UNICAMP), Brazil

rodolfo.azevedo@unicamp.br

http://www.ic.unicamp.br/~rodolfo/mo801

Goal of this class

Module 6, Class 4: the full stack in one picture, where to go next, and course feedback.

Every component in the system you built today was described in the first three weeks of the course. Today we draw the line from the first logic gate to the last inference result.

At the end of this class, you should be able to:

• Trace the complete abstraction stack from Boolean logic gates to a working AI inference result.
• Identify the key hardware/software design decisions made at each module of the course and their performance consequences.
• Explain how each layer's latency contribution adds up to the total inference time measured in Project 3.
• Describe concrete next steps in computer architecture, ML hardware, or embedded systems based on your interests.

The full abstraction stack

Boolean logic (M01A01)
    AND, OR, NOT, XOR → truth tables → Boolean algebra
    │
    ▼
Combinational circuits (M01A01-A02)
    MUX, decoder, comparator → `assign`, `always_comb`
    │
    ▼
Sequential circuits (M01A03-A04)
    DFF → register → counter → FSM → `always_ff`, `enum`
    │
    ▼
Digital building blocks (M01A05)
    ALU, register file, SRAM → `parameter`, `generate`
    │
    ▼
RV32I processor (M02)
    ISA → multicycle datapath → control FSM → `ebreak` → simulation
    │
    ▼
HW/SW interface (M03)
    Bus → Zmmul → Zicsr/Zicntr → CMAC → UART → timer → GPIO → C drivers
    │
    ▼
TinyML inference (M04)
    tiny_conv → int8 quantization → C kernel → profiling → roofline
    │
    ▼
Hardware accelerator (M05)
    MAC array → BRAM buffer → FSM → bus integration → speedup measurement
    │
    ▼
KWS inference on Tang Nano 9K
    "yes" / "no" / "_unknown_" / "_silence_"

Every layer was built by you, from scratch. None of them were black boxes.

What Nand2Tetris spirit looks like for AI

Nand2Tetris takes you from a NAND gate to Tetris. This course takes you from an AND gate to AI inference.

The key difference: this course's "application" is a machine learning model — which means understanding not just the compute, but the data representation (int8 quantization), the memory hierarchy (BRAM vs. DMEM vs. bus), and the performance model (roofline).

What you now understand that documentation alone cannot teach

1. Why RISC-V has 6 instruction formats — you implemented the immediate extraction logic for each.
2. Why memory-mapped I/O needs volatile — you saw what the compiler does without it.
3. Why the bottleneck is memory, not compute — you measured it, not just read about it.
4. Why Amdahl's Law limits system speedup — you lived it: 7.2× layer, 3.5× system.
5. Why the BRAM buffer mattered more than the extra MACs — you placed both on the roofline.
6. Why TinyML uses int8, not float32 — you implemented the requantization arithmetic.

These are not things you can fully understand without building. The course existed to create the experience of building.

Limitations of what we built

Honest accounting of what a production system does that ours does not:

None of these gaps are conceptual — they are engineering. You have the foundation to close any of them.

Research directions from here

Hardware/software co-design: model architecture search that explicitly optimizes for your hardware constraints — fewer channels, fewer layers, compatible with a 4-wide MAC array.

In-memory computing: instead of moving weights from SRAM to MAC units, perform the multiplication inside the memory cell (analog or digital). Eliminates the memory bottleneck entirely. Active research area.

Dataflow compilation (TVM, MLIR/CIRCT): compilers that take a model graph and generate both the software schedule and the hardware configuration automatically. What Vela does for Ethos-U.

Neuromorphic computing: spiking neural networks (SNNs) — binary activations, event-driven computation, ultra-low power. Very different trade-off point from the int8 MAC-array world.

Open-source silicon (OpenROAD, efabless): take your accelerator design all the way to a real chip. The GW1NR-9C costs $3 per unit; your chip could cost $0.10 in volume if you tape it out in the Skywater 130nm open PDK.

The open-source ecosystem

Everything used in this course is free and open:

You can keep going after this course without spending money on tools.

Course feedback

(Anonymous — please be specific)

1. Which module was most valuable? Which was least?
2. What was the biggest obstacle you encountered?
3. What would you add, remove, or restructure?
4. Did the Tang Nano 9K board exercises help? Too many? Too few?
5. Was the difficulty level appropriate?

Your feedback directly shapes the next offering of this course.

Thank you

You built a processor from logic gates, extended it with hardware peripherals, ran a machine learning model on it, and designed custom silicon to accelerate it — all in one semester, on a $20 FPGA board.

That is the course. You now know what is inside the devices that surround you every day.