@inproceedings{yup-hay-06-aa-bitwd,
  author = {Pu, Yu and Ha, Yajun},
  title = {An Automated, Efficient and Static Bit-Width Optimization Methodology towards Maximum Bit-Width-to-Error Tradeoff with Affine Arithmetic Model},
  booktitle = {Proc. of the 2006 Asia and South Pacific Design Automation Conference (ASP-DAC '06)},
  year = 2006,
  publisher = {IEEE Press},
  pages = {886--891},
  numpages = {6},
  location = {Yokohama, Japan},
  doi = {10.1145/1118299.1118500},
  abstract = {Ideally, bit-width analysis methods should be able to find the most appropriate bit-widths to achieve the optimum bit-width-to-error tradeoff for variables and constants in high level DSP algorithms when they are implemented into hardware. The tradeoff enables the fixed-point hardware implementation to be area efficient but still within the allowed error tolerance. Unfortunately, almost all the existing static bit-width analysis methods are Interval Arithmetic (IA) based that may overestimate bit-widths and enable fairly pessimistic bit-width-to-error tradeoff. We have developed an automated and efficient bit-width optimization methodology that is Affine Arithmetic (AA) based. Experiments have proven that, compared to the previous static analysis methods, our methodology not only dramatically reduces the fractional bit-width by more than 35{\%} but also slightly reduces the integer bit-width. In addition, our probabilistic error analysis method further enlarges the bit-width-to-error tradeoff.}
}