@article{doi-hor-nak-kim-06-aa-bitlen,
  author = {Doi, Noburo and Horiyama, Takashi and Nakanishi, Masaki and Kimura, Shinji},
  title = {Bit-Length Optimization Method for High-Level Synthesis based on Non-Linear Programming Technique},
  journal = {IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences},
  year = 2006,
  volume = {E89-A},
  number = {12},
  pages = {3427-3434},
  month = 12,
  doi = {10.1093/ietfec/e89-a.12.3427},
  comment = {Considers conversion of a C program with float variables to a digital circuit with fixed-point variables. Uses AA to propagate errors.},
  abstract = {High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.}
}