@entry{ben-cho-pur-bon-18-ab-fpgabits,
  author = {V Benara and Z Choudhury and S Purini...},
  title = {Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths},
  journal = {arXiv preprint arXiv ...,},
  volume = {},
  number = {},
  pages = {},
  year = 2018,
  month = ,
  doi = {},
  comment = {},
  abstract = {},
  url = {{\url{https://arxiv.org/abs/1803.02660}}},
  quotes = {... easily deploying any kind of interval/affine arithmetic based range analyses in the DSL compiler. Thirdly, we show that interval/affine arithmetic based techniques fail to take into account ...}
}