@entry{wan-zha-yan-18-aa,
  author = {P Wang and Y Zhang and J Yang},
  title = {Research and design of AES security processor model based on FPGA},
  journal = {Procedia computer science,},
  volume = {},
  number = {},
  pages = {},
  year = 2018,
  month = ,
  doi = {},
  comment = {},
  abstract = {},
  url = {{\url{https://www.sciencedirect.com/science/article/pii/S1877050918305908}}},
  quotes = {... This design using finite field multiplication inverse and affine arithmetic is constructed as follows the S box module diagram, as shown in Fig. 2, the box also applies to inverse S box S ...}
}