@inproceedings{lee-gaf-men-luk-05-aa-bitwidth,
  author = {Lee, Dong-U and Gaffar, Altaf Abdul and Mencer, Oskar and Luk, Wayne},
  title = {{MiniBit}: {Bit}-Width Optimization via Affine Arithmetic},
  pages = {837--840},
  year = 2005,
  doi = {10.1145/1065579.1065799},
  abstract = {MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20{\%} and 12{\%} respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA.},
  booktitle = {Proceedings of the 42nd Annual Design Automation Conference (DAC'05)},
  publisher = {Association for Computing Machinery},
  isbn = {1595930582},
  keywords = {FPGA, simulated, bit-width, annealing, affine arithmetic, fixed-point},
  location = {Anaheim, California, USA}
}