@inproceedings{cou-bha-luk-con-car-din-pet-12-aa-fpga,
  author = {Coutinho, Jose G. F. and Bhattacharya, Sujit and Luk, Wayne and Constantinides, George A. and Cardoso, João M. P., and Carvalho, Tiago and Diniz, Pedro C. and Petrov, Zlatko},
  title = {Resource-Efficient Designs using an Aspect-Oriented Approach},
  booktitle = {Proceedings of the 15th IEEE International Conference on Computational Science and Engineering (CSE)},
  pages = {399-406},
  doi = {10.1109/ICCSE.2012.62},
  year = 2012,
  month = dec,
  comment = {Optimization of FPGA designs. Mentions AA but does not use it?},
  abstract = {The increasing capability and flexibility of reconfigurable hardware, such as Field-Programmable Gate Arrays (FPGAs), give developers a wide range of architectural choices that can satisfy various non-functional requirements, such as those involving performance, resource and energy efficiency. This paper describes a novel approach, based on an aspect-oriented language called LARA, that enables systematic coding and reuse of optimisation strategies that address such non-functional requirements. Our approach will be presented in three steps. First, this approach is shown to support design space exploration (DSE) which makes use of various compilation and optimisation tools, through the deployment of a master weaver and multiple slave weavers. Second, we present three compilation and synthesis strategies for word-length optimisation based on this approach, which involve three tools: the WLOT word-length optimiser deploying a combination of analytical methods, the AutoESL tool compiling C-based descriptions into hardware, and the ISE tool targeting Xilinx devices. Third, the effectiveness of the approach is evaluated. In addition to promoting design re-use, our approach can be used to automatically produce a range of designs with different trade-offs in resource usage and numerical accuracy according to a given LARA-based strategy. For example, one implementation for a sub band filter in an MPEG encoder provides 31{\%} savings in area using non-uniform quantizers when compared to a floating-point description with a similar error specification at the output. Another fixed-point implementation for the grid Iterate kernel used by a 3D path planning application consumed 25{\%} less resources when the error specification is increased from $10^{-6}$ to $10^{-4}$.}
}