Calendar
Dates are not fixed here — the official 2026s2 Unicamp calendar will have holidays that shift class numbers. Use this table as the sequence of 30 classes; map to actual dates once the calendar is published.
| Class | Module | Topic | Seminar | Milestone |
|---|---|---|---|---|
| 1 | M00 - Introduction | Course roadmap; the AI-at-the-edge landscape; KWS live demo: "how many instructions does this take?" — motivation for the whole course | — | Lab 1 out — train & run KWS on your PC |
| 2 | M01 - Digital Design & SV | Combinational logic recap + SV: assign, operators, vectors → first synthesis on the Tang Nano 9K (LED = button function) |
— | Lab 1 due / Lab 2 kickoff — install OSS CAD Suite |
| 3 | M01 - Digital Design & SV | Combinational building blocks (MUX, decoder, comparator) + always_comb, case |
S1 | Lab 3 out — decoder on the Tang Nano 9K |
| 4 | M01 - Digital Design & SV | Sequential logic (flip-flops, registers, timing) + always_ff, blocking vs. non-blocking |
S2 | Lab 3 due |
| 5 | M01 - Digital Design & SV | FSMs (Mealy/Moore) + enum, struct em SV |
S3 | Lab 4 out — traffic light FSM on the Tang Nano 9K |
| 6 | M01 - Digital Design & SV | Building blocks (ALU, register file, BRAM) + parameter, generate |
S4 | Lab 4 due |
| 7 | M01 - Digital Design & SV | Verification + Verilator testbenches + full toolchain flow (Yosys → nextpnr → openFPGALoader) | S5 | Lab 2 due |
| 8 | M02 - RISC-V Architecture | RV32I ISA: registers, instruction formats, immediate encoding, memory model | S6 | — |
| 9 | M02 - RISC-V Architecture | The multicycle datapath: fetch, decode, execute, memory, write-back | S7 | — |
| 10 | M02 - RISC-V Architecture | Designing the control FSM: states, walkthroughs of ADDI, LW, BEQ |
S8 | — |
| 11 | M02 - RISC-V Architecture | Verification strategy; compiling C to RV32I; ebreak convention; synthesis & timing |
S9 | Project 1 kickoff |
| 12 | M02 - RISC-V Architecture | From C to bits: everything becomes an instruction; measuring performance with a cycle counter; KWS cycle estimate as motivation | S10 | Lab 5 out — -O0 vs -O2 cycle count on the board |
| 13 | M02 - RISC-V Architecture | Project 1 — lab session & Q&A | S11 | — |
| 14 | M02 - RISC-V Architecture | Project 1 — lab session & Q&A | S12 | Project 1 due |
| 15 | M03 - HW/SW Interfaces | Memory-mapped I/O and minimal on-chip bus; the memory map design | S13 | — |
| 16 | M03 - HW/SW Interfaces | ISA extensions (Zmmul, Zicsr, Zicntr) + custom instruction (CMAC); alternative HW/SW interfaces | S14 | — |
| 17 | M03 - HW/SW Interfaces | Peripheral design: UART, timer/cycle counter, GPIO; drivers in C | S15 | Project 2 kickoff |
| 18 | M03 - HW/SW Interfaces | Integration & verification of the extended platform | S16 | — |
| 19 | M04 - TinyML on the Edge | TinyML landscape; the KWS model: tiny_conv, int8 quantization, MFCC features | S17 | Lab 5 due / Lab 6 out — KWS kernel deep dive |
| 20 | M04 - TinyML on the Edge | The dependency-free inference kernel in C: MAC, conv, int8 arithmetic | S18 | Project 2 due |
| 21 | M04 - TinyML on the Edge | Profiling on your CPU: finding the bottleneck layer; cycle counts per operation | S19 | Lab 7 out — KWS kernel profiling |
| 22 | M04 - TinyML on the Edge | Design space for the accelerator: interface styles, memory bottleneck, resource budget | S20 | Lab 6 due / Lab 7 due / Project 3 kickoff |
| 23 | M05 - AI Accelerators | Accelerator datapath: int8 MAC array, local buffers, tiling strategy | — | — |
| 24 | M05 - AI Accelerators | Implementing and verifying the accelerator in SystemVerilog | — | — |
| 25 | M05 - AI Accelerators | Integrating the accelerator via the Project 2 memory-mapped interface; end-to-end measurement | — | — |
| 26 | M05 - AI Accelerators | Roofline model and arithmetic intensity: is your speedup compute- or memory-bound? | — | — |
| 27 | M06 - Closing | Off-the-shelf alternatives: RVV, Arm Ethos-U, GPUs — how do they compare to what you built? | — | — |
| 28 | M06 - Closing | Final project presentations & demos (Part 1) | — | — |
| 29 | M06 - Closing | Final project presentations & demos (Part 2) | — | Project 3 due |
| 30 | M06 - Closing | Retrospective: the full stack from gates to AI; where to go next | — | — |
Legend
- Seminar (S1–S20): individual weekly student presentation, embedded in the class. See Seminars for topic suggestions per module.
- Lab 1–7: hands-on exercises. Lab 1 (KWS on PC) and Lab 2 (toolchain) have longer deadlines; Labs 3–4 are short exercises (due the following class); Labs 5–7 accompany Modules 2 and 4. Lab 6 (KWS kernel) is released at Class 19; Lab 7 (profiling) is released at Class 21 and due at Class 22.
- Milestone: project deliverables and lab checkpoints — see Projects and Labs.