Skip to content

Project 1 - A RISC-V Core

In this project, you will design a simple multicycle RV32I processor in synthesizable SystemVerilog, verify it, and run it on a real Tang Nano 9K FPGA. This core is the foundation for every later project in the course: the peripherals, the ISA extensions, and ultimately the accelerator will all be attached to it.

Objectives

  1. Implement a multicycle RV32I processor in synthesizable SystemVerilog.
  2. Build a Verilator-based testbench to verify instruction-level correctness.
  3. Synthesize the design for the Tang Nano 9K using the OSS CAD Suite (Yosys + nextpnr-himbaechel) and run it on real hardware.
  4. Execute simple C programs (compiled to RV32I) on your core.

Specification

Your processor must implement the RV32I base integer instruction set (the M extension is not required here - it is added as an ISA-extension exercise in Project 2).

The implementation must be multicycle: each instruction may take a different number of clock cycles to execute. You may take inspiration from the multicycle datapath in Patterson & Hennessy's Computer Organization and Design, adapted to RISC-V (see Harris & Harris, Digital Design and Computer Architecture, RISC-V Edition).

You may use an existing toolchain or build your own (riscv-gnu-toolchain) to compile C programs to RV32I binaries. An online assembler is also acceptable for smaller test programs.

Use the ebreak instruction as your program-termination convention.

Your code must be synthesizable: it must be possible to generate a real circuit from it. Functional verification should use Verilator testbenches; synthesis and place-and-route should use Yosys and nextpnr-himbaechel (Gowin backend) from the OSS CAD Suite, with bitstream upload via openFPGALoader. See Lab 2 for toolchain setup.

You are encouraged - but not required - to demonstrate program execution observably on the board (e.g., via LEDs, a 7-segment display, or UART output if you get ahead on Project 2).

Deliverables

  • SystemVerilog source for the processor.
  • Verilator testbench(es) covering the implemented instructions.
  • Build scripts for synthesis/place-and-route/bitstream generation targeting the Tang Nano 9K.
  • At least one C program, compiled and executed on real hardware, with evidence of correct execution (e.g., register dump, simulation trace, or on-board observation).
  • Documentation of your processor's architecture (datapath diagram, FSM, supported instructions).

Submission

Work in pairs (see Home). Submit via GitHub Classroom (link provided via Google Classroom). Due: see Calendar.

Evaluation criteria

  1. Coverage of RV32I instructions.
  2. Correctness and clarity of the multicycle datapath and control FSM.
  3. Quality and coverage of the verification testbenches.
  4. Successful synthesis and execution on the Tang Nano 9K.
  5. Use of git for tracking and submitting your work.
  6. Documentation of the implemented processor.
  7. Extra tests or features beyond the minimum specification.