Labs Overview
Labs are short, hands-on guides that get you set up for the projects. Unlike projects, labs are not graded individually, but completing them on schedule is necessary to keep up with the projects.
| Lab | Week | Topic |
|---|---|---|
| Lab 1 — KWS on your PC | 1 | Train, quantize, and run a keyword-spotting model on your PC — see the end goal before building the hardware |
| Lab 2 — Toolchain & FPGA bring-up | 2 | Install the OSS CAD Suite, build/upload a minimal design to the Tang Nano 9K |
| Lab 3 — SystemVerilog basics | 3 | SystemVerilog constructs you'll use in Project 1, and which subset is synthesizable |
| Lab 4 — Traffic light FSM | 5–6 | Implement and verify a Mealy/Moore FSM on the Tang Nano 9K |
| Lab 5 — Cycle counting on your CPU | 12 | Use the rdcycle CSR to measure -O0 vs -O2 performance on your RISC-V board |
| Lab 6 — KWS kernel deep dive | 19 | Read and run the dependency-free int8 inference kernel; trace the MAC loop and requantize function |
| Lab 7 — KWS kernel profiling | 21–22 | Instrument conv_int8 with hardware cycle counters; identify the bottleneck layer; compute cycles per MAC |
Notes
- Labs 1–2 have longer deadlines spanning multiple classes; Labs 3–4 are short exercises due the following class.
- Labs 5–7 accompany Modules 2 and 4 and feed directly into Projects 2 and 3.
- Lab 6 can be started on your PC without hardware; Lab 7 requires Project 2 working (UART + cycle counter on your board).
- See the Calendar for exact release and due dates.